1. Field of the Invention
The present invention relates generally to the high speed electronic devices, and more particularly, to a method and system for calculating the high frequency capacitance and high frequency inductance limits (two separate, but connected problems) in two-dimensional (2D) on-chip interconnect structures.
2. Description of the Prior Art
High-speed electronic devices on silicon chips successfully operate today at frequencies up to 100 HGz, considering technologies such as SiGe and SOI. Coplanar transmission lines turn to be important on-chip interconnects for such devices. In order to have a model for coplanar structures on silicon substrates, the following low frequency and the high frequency limit values of the following electrical parameters have to be calculated: static capacitance C0, infinite (high frequency limit) capacitance C∞, low frequency inductance L0 and infinite (high frequency limit) inductance L∞. In addition to this, the low and high frequency values of the resistance and shunt conductance have to be calculated as well. Prior art techniques for capacitance and inductance calculation were developed mostly for calculation of the low frequency (static) capacitance C0 and low frequency inductance L0, since prior art applications were mainly for lower frequencies, where modeling of the static values is sufficient. The high frequency limit capacitance becomes important for transmission lines, or any metal conductor structures right above the silicon substrate at high frequencies (several GHz and higher) in which the silicon behaves as a dielectric material rather than like a metal. As is apparent from prior art teachings described in commonly-owned, co-pending United States Patent Publication No. 2005/0262458 filed on May 6, 2005 entitled “Modeling Capacitance of On-chip Coplanar Transmission Lines Over the Silicon Substrate”, existing closed-form expressions for the coplanar transmission line high frequency limit capacitance are quite complex, and their accuracy is not always sufficient. Numerical calculations are time and memory consuming and may not be stable Moreover, the existing prior art solutions requires usage of an EM solver as described in the aforementioned United States Patent Publication No 2005/0262458. EM solver calculations are time consuming and may have convergence problems.
In commonly-owned, co-pending United States Patent Publication No. 2006/0286691 there was described methods for calculating the static capacitance. In the low frequency limit of US20060286691 the silicon is treated as a metal.
In commonly-owned, co-pending United States Patent Publication No. 2005/0262458 there is described a methodology that addresses the same problem of calculating the high frequency limit capacitance but using a very different imaging method, which is not based on a field lines approach. The method described in US 2005/0262458 is very complex. Moreover, none of these cited prior art references teach or suggest a method for the calculation of the high frequency limit inductance.
What would be highly desirable is to provide field based expressions for deriving and calculating high frequency capacitance C∞ and inductance L∞ of a coplanar transmission line structure over the silicon substrate, which are very compact and have the desired accuracy for many applications.